Module
Pipelining
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About
Classic 5-stage pipeline (IF/ID/EX/MEM/WB), hazards (structural, data, control), forwarding, stalling, branch prediction basics, and pipeline performance. Core of modern CPU microarchitecture at undergrad depth.
Goal
Pipeline a RISC datapath; detect and resolve hazards with forwarding and stalls; compute speedup and CPI impact of hazards and stalls; explain basic static/dynamic branch prediction and its effect on control hazards.
Prerequisites
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