Module
Virtual Memory and the Full Memory Hierarchy
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About
Paging, TLBs, page tables, interaction of TLB/cache/VM, and how the OS and hardware cooperate. Completes the memory hierarchy picture for CS majors.
Goal
Explain address translation with TLB and page table; compute effective access time with TLB misses; describe page fault handling at a high level and cache/TLB interactions (VIVT, VIPT, etc. at conceptual level).
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